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Instantiate a clock inside a verilog component | Cypress Semiconductor

Instantiate a clock inside a verilog component

Summary: 2 Replies, Latest post by Bob Marlowe on 14 Jun 2013 03:04 PM PDT
Verified Answers: 0
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Rocketmagnet's picture
131 posts


I am creating a Verilog component which requires a clock. I would like this to be an internal clock, so that the user doesn't need to concern themselves with it.


I have seen some components (eg PWM) which have the option of an internal clock. This is implemented by using a schematic component containing the clock plus another verilog component.


Is it possible instead to simply instantiate a clock within the Verilog?

user_78878863's picture
2551 posts

AFAIK you need the external clock. This is because PSoC needs to allocate a clock resource for that (e.g. a divider), and this is something separate from the UDB. So you will need a schematic component for that.

user_1377889's picture
9268 posts

There is no VeriLog instruction that creates a clock and sets its frequency, Easiest would be to connect a clock to your component and use that a s a macro or wrap it into a schematic component.




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