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I2C with 3.3V pull-ups and PSoC3 5.0V operation | Cypress Semiconductor

I2C with 3.3V pull-ups and PSoC3 5.0V operation

Summary: 1 Reply, Latest post by pvkv on 16 Mar 2016 07:36 AM PDT
Verified Answers: 0
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rdonahoo1_1583441's picture
6 posts

The component documentation has a note about reliable logic transitions on the I2C bus.

I2C_v3_50.pdf states: 

"Note The default threshold voltages for the Pins component is CMOS. When the I2C lines are pulled up to 3.3 V and the PSoC is running on 5.0 V, the CMOS threshold levels may not guarantee reliable logic transitions. In this case, the SCL and SDA pin component thresholds should be set to TTL."

The options I see for the pins I have assigned for SDA and SCL don't show a TTL option to select for the input pin threshold.  I can select from the following values for input threshold in the drop-down menu:

  • CMOS
  • Vddio
  • 0.5xVref
  • Vref

I'm using PSoC Creator  3.3 CP2 ( released 03/01/2016 and have 4.99k pull-up resistors connected to 3.3V on the SDA and SCL lines.  Which threshold should I select to guarantee reliable logic transitions?


P.S.  I2C bus speed is set to 400kbps.  Seems that these pull-ups are too large based on what's shown in the component documentation.

pvkv's picture
Cypress Employee
82 posts


It is LVTTL. It gives you VIH = 2 V and VIL = 0.8. 

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