Grant Allocation Fairness Algorithm | Cypress Semiconductor
Grant Allocation Fairness Algorithm
TRM explains about Grant Allocation fairness Algorithm, but the description is not sufficient is what I feel.
Here is a little more explaination of this algorithm.
"In this method, the channel 0 and 1 take highest priority and no other prior-ity can interrupt the channels with priority 0 and 1.A DMA Channel of priority 0 and priority 1 occupy the bus 100%. Rest of the priorities share the bus based on the number of channels requested at that time. Because pri-ority 0 has higher priority than 1, priority 0 can interrupt priority 1.
In both the cases, a DMA channel of low priority can be interrupted by a high priority channel only during the source engine phase.
Under ideal conditions the Arbitration phase takes one cycle.
The channels with priorities 2-7 are given the access according to Table
Priority Level Bus Allocation Percentage
When DMA channels of varied priority request for DMAC at a time, 100% of bus bandwidth will be allocated for channels of priority 0 or 1. Table applies only if DMA channels with priorities 2-7 are requesting simultaneously. Otherwise, the DMA channel with higher priority is given more access than Table shows.Attached file shows a channel priority wheel that describes how the next 63 requests are handled if all channels with priorities 2 to 7 are requesting simultaneously"
If a channel with priority 2 to 7 is NOT requesting, the slots of the missing channel priority are used by the channel with the highest priority. In that case, channels with higher priority get more access than channel priority wheel shows."