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Dual Ported SRAM DMA Access? | Cypress Semiconductor

Dual Ported SRAM DMA Access?

Summary: 4 Replies, Latest post by McBadger on 22 Oct 2014 01:47 PM PDT
Verified Answers: 0
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user_377526869's picture
13 posts

 The PSoC 3 CY8C38 Family Datasheet says:

  • Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed. 

It also says in PHUB Features:


  • Simultaneous CPU and DMA access to peripherals located on different spokes 

I notice though that it only lists one PHUB Spoke (0) for SRAM.

What I'd been wondering, if I have a Group 1 UDB on Spoke 6, and a Group 2 UDB on Spoke 7, would they be able to DMA concurrently to different 4KB SRAM blocks?






user_78878863's picture
2551 posts

AFAIK there can only be one DMA transaction at a given time. They might be interleaved, but not really concurrently.

user_1377889's picture
9268 posts

The given explanation tells about CPU and DMA access which can be done simultaneously under some restrictions. Simultan accesses of different DMA spokes is not implemented, they always will be performed at different machine - cycles.

Can you tell us a bit more what you would like to perform and why the simultan working is so evident for your project?



user_14586677's picture
7646 posts

The CPU has a direct connection to SRAM without going
through the PHUB. In addition to faster SRAM access by the
CPU, this allows for simultaneous accesses to SRAM by
both the CPU and the PHUB DMA controller, because
SRAM is physically implemented as multiple separate
blocks. If the CPU and the PHUB are accessing separate
blocks, they both have simultaneous unimpeded access.
In case of contention, the following applies:

CY8C38 family – The 8051 has priority over the PHUB
for the lower and upper 4 KB (SRAM BANK0 and
BANK2), and the PHUB has priority over the CPU for the
middle 4 KB (SRAM BANK1). When DoC tracing is
active, the DoC has exclusive access to the upper 4 KB
(SRAM BANK2) – neither the CPU nor the PHUB can
access this bank while tracing is active.

The SRAM responds to CPU, PHUB, and DoC accesses
with zero wait states for both reads and writes as long as the
access does not lose priority arbitration. Arbitration is done
on a cycle-by-cycle basis at the time of SRAM access. The
losing master is held off until the winning master has fin
ished accessing the SRAM block; the losing master gains
access on the cycle immediately after.


From TRM.


Regards, Dana.

user_377526869's picture
13 posts

 Thanks for the explanations.

I thought I'd read somewhere that simultaneous was possible, but really it's that for optimal performance you want source and dest to be on different spokes, so that you can do cut-through, rather than store-and-forward.

I've got a ping-pong buffer scheme, and have the flow setup like this:

UDBa -> RAMBuf0

RamBuf1->UDBx, RamBuf1->UDBy

And I had been wondering if I should do custom UDB placement to make sure that UDBa is not in the same place as UDB[xyz], so that they could go simultaneously at a high bit rate. Looks like it's not possible, so placement doesn't matter.




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