Dual Ported SRAM DMA Access? | Cypress Semiconductor
Dual Ported SRAM DMA Access?
The PSoC 3 CY8C38 Family Datasheet says:
- Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed.
It also says in PHUB Features:
- Simultaneous CPU and DMA access to peripherals located on different spokes
I notice though that it only lists one PHUB Spoke (0) for SRAM.
What I'd been wondering, if I have a Group 1 UDB on Spoke 6, and a Group 2 UDB on Spoke 7, would they be able to DMA concurrently to different 4KB SRAM blocks?