Digital Filter Block Clarifications | Cypress Semiconductor
Digital Filter Block Clarifications
I am trying to learn more about the Digital Filter Block (DFB) to use in my application. I am interested in using the DFB to perform a hardware PID calculation because it seems to be a very powerful tool that will not use up as many resoucres as other implementations.
I have read through the DFB datasheet and the DFB section in the TRM, but I am a little confused with some of the descriptions. I am trying to walk through the DFB example project included with Creator to learn how and why the developer programed the DFB, however, while stepping through this code I have hit a wall. On line 6 of the DFB assembler code, the developer used the jpml() instruction with the condition "in1". On page 38 of the DFB datasheet the description for 'in1' mentions a 'Channel 1 Input Register', but I cannot find a reference to this register anywhere else in the DFB manual or TRM. I looked for a 'Channel 1 Input Register' on the diagram on page 22, but only found a 'Stage A/B' register. Are these the same thing?
Am I looking in the wrong place? From my understanding of the code, the 'jmpl()' instruction will not execute until the condition is met, but I don't know how to put an entry into that register. Can anyone help me out?
For clarity I included the example project as an attachment below.