Delta Sigma ADC very noisy at the top end of its range | Cypress Semiconductor
Delta Sigma ADC very noisy at the top end of its range
I'm trying to work out why my delta sigma ADC seems to be very noisy towards the top end of its range (3000 / 4095). My ADC is set up as follows: Single Sample, 12-bits, 40000SPS, Single ended input mode, Vsssa to 1.25v, Buffer Gain 1, Rail to Rail, Vref = Vdda/4. I have 12 PSoC pins connected to an analogue multiplexer, and am using a simple RC filter on each input pin.
When the input voltages are low (around 500/4095) there is very little noise, sometimes it can be as low as 1.5 LSB. But around 2000/4095, I can see around 6-10 LSB. By 3000/4095, I can see about 20LSB noise!
I'm using separate analogue and digital linear regulators with ferrite bead filters. I have a continuous ground plane under the PSoC. I have also read the several application notes on achieving good ADC performance, and I believe I am following all of the advice.
Is this amount of noise to be expected, or am I doing something wrong?