CY8CDVK-001 I/O Voltage limit? | Cypress Semiconductor
CY8CDVK-001 I/O Voltage limit?
1) I am working with the CY8C3866AXI-040 (100-TQFP) chip that is the standard module on the PSoC 3 DVK-001. This chip is the production chip. It appears that on my DVK, the Vadj voltage CAN'T be brought lower than 2.0V. Is this part of the design/correct?
2) I want to assess the ability of the PSoC 3's I/Os to reach their stated ability of 1.2V lower range. However, online sources say that this can only go as low as 1.8V. Which is true?
3) Is there any change in slew rate or drive characteristics at lower voltages? Is there anything I should know about this when designing with low I/O voltages?
3) What is the frequency limit on the PSoC 3's I/O pins? I understand that there is a different input/output frequency limit. However, I don't understand why this is, and what the limitations are.