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Countcell counters in PSoC 3/5LP UDB. | Cypress Semiconductor

Countcell counters in PSoC 3/5LP UDB.

Summary: 0 Replies, Latest post by rahulram on 21 Mar 2013 01:16 AM PDT
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rahulram's picture
Cypress Employee
115 posts


Are you running out of counters/Timer/PWMs in the PSoC UDB due to the Datapath resources being utilized? Thes countcell counters will come in to a rescue then. These counters use the control cells in the UDB, and hence we have a privilege to use 24 of them in PSoC3/5LP architecture. The control cells shall either be used as a control register or as a 7 bit counter lilke this.

Remember that these are 7 bit counters that counts down and not 8 bits.

To get this counter up and running, we need to instantiate the following code,




/* input */ .clock(clk),

/* input */ .reset(reset),

/* input */ .load(1'b0),

/* input */ .enable(enable),

/* output [06:00] */ .count(count2),

/* output */ .tc(tc1)


Just hook up the appropriate inputs to this module and get the counter running.  A very important point to remember here is that, to enable this counter, we need to enable the counter both in the hardware and also in the software. In hardware, the enabling happens, when the appropriate enable signal is hooked up in the module above. To enable the counter in the software, we have to set the 5th bit in the Auxiliary control register. To do that, open the "cyfitter.h" and figure out the appropriate Auxiliary register for that instance and write a 1 to the 5th bit. The register will look like the one shown below


countcell_1_cnt7_counter__CONTROL_AUX_CTL_REG |= 0x20;

This will enable the counter in software.

Happy designing,

Rahul ram

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