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A Cool PSoC Application - Voltage Controlled Oscillator | Cypress Semiconductor

A Cool PSoC Application - Voltage Controlled Oscillator

Summary: 1 Reply, Latest post by Archimedes on 28 Nov 2011 12:58 PM PST
Verified Answers: 0
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dasg's picture
Cypress Employee
730 posts

With a handful of PSoC3 resources and an external capacitor, a Voltage controlled oscillator can be created.

Pin "Cint" is configured as both Digital and Analog pin with a drive mode Open Drain drives low. When output of Comparator is High, IDAC output is connected to the pin.  When comparator output is Low, the pin shorts to Ground.

IDAC – configured as a source – charges an external capacitor connected to "Cint". When the capacitor voltage crosses input voltage Vin, comparator output becomes low (comparator is set for inverted logic) and discharges the capacitor. As capacitor voltage becomes zero, the comparator output becomes high and IDAC starts charging the capacitor. The cycle continues and we get an oscillator whose frequency is inversely proportional to Vin.  The circuit has excellent “Period vs. Vin” linearity.

For a given input voltage, the combination of IDAC value and external capacitor determines the maximum Period (1/f) of the output.  We know that when a capacitor is charged using a constant current, the time taken to charge to a known voltage is

t = C * V / I

For example, if the maximum period value is desired to be 500uS for an input voltage of 2.5V, for an IDAC value of 1uA, the value of C can be calculated:

C = (500uSec * 1uA) / 2.5V = 200pF

The comparator is synchronized to a clock.  The period of the clock should be long enough to discharge the capacitor.  Too high a clock frequency, the capacitor may not discharge completely.  Too low a clock frequency, the % of the "discharge time" to "charge time" will increase and will reduce the linearity.  The value of the clock will also depend on the value of the capacitor.  Higher value of capacitor will require a longer discharge time.

Selecting the right combination of IDAC, Capacitor and the SyncClock is an interesting exercise left to the user.

user_114239718's picture
23 posts

There is a small trouble with this method... The frequency/period changes with the voltage Vin. But with the period the waveform duty cycle would also be affected.

A good way might be to use the polarity control on the IDAC and charge and discharge the cap with a similar current. this would require the comparator to switch between two voltage thresholds. Changing the delta of the voltages would change the frequency. This would be a voltage controlled frequency which has a constant duty cycle.

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