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Clock for ADC | Cypress Semiconductor

Clock for ADC

Summary: 1 Reply, Latest post by PSoC73 on 02 Aug 2013 08:40 PM PDT
Verified Answers: 0
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sergiakalorth's picture
4 posts


Dear All,

While reading the appnote AN77900, PSoC® 3 and PSoC 5LP Low-power Modes and Power Reduction Techniques, in page 5 is stated, or I understand, that the clock value of the Master Clock needs to be higher than the value for the ADC.

I was testing something that shouldn't work but I don't get an error (see the image attached). You can see that I've deliberately lowered the clock... How can this not show a warning?



user_119377051's picture
866 posts

Hi sergiakalorth,

Clock editor of Creator still has a small bug.

For example, when nominal clock frequency is much different with desire frequency,

It been not warning.

Workspace explore / result TAB / ...timing.html (Static Timing Analysis)

is provide othe static report. Is it something help for you?

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