Clock for ADC | Cypress Semiconductor
Clock for ADC
While reading the appnote AN77900, PSoC® 3 and PSoC 5LP Low-power Modes and Power Reduction Techniques, in page 5 is stated, or I understand, that the clock value of the Master Clock needs to be higher than the value for the ADC.
I was testing something that shouldn't work but I don't get an error (see the image attached). You can see that I've deliberately lowered the clock... How can this not show a warning?