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ADC to UART: Do I need a buffer? | Cypress Semiconductor

ADC to UART: Do I need a buffer?

Summary: 8 Replies, Latest post by hli on 20 Aug 2013 06:59 AM PDT
Verified Answers: 0
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user_134344396's picture
56 posts

My overall goal is to sample two signals at 30 ksps / signal (60 ksps total) and send the data via a wireless protocol such as bluetooth.

Current progress:

I'm able to sample one signal at 10 ksps using a 8-bit delta sig ADC. I'm able to send a few seconds of data at 10 ksps to the pc via UART. I may need to configure an external clock to get the required baud rate to match my hardware for 30 ksps.

My code currently sends one byte after each ADC conversion. I don't think that this is the best way, and I'm afraid it won't work well for 30-60 ksps.


  1. Should I be using some kind of buffer to store data before sending it via UART?
  2. What's the best way to send streaming data via UART?
  3. Will I be able to two channel's worth of data (60 ksps) using UART without issue?
  4. Would you suggest that I use a serial-to-bluetooth module to make this design wireless? I've never used bluetooth, but the data rate seems to be ok for this application.
user_1377889's picture
9241 posts

As usual the answere is : That depends...

If you are continously sending your data via an UART check first if all the bits can pass.

Let us estimate: 60 ksmp/s times 12 (for the overhead like stop-bits etc) that is 720kbaud. That's a lot and I question if that would be possible.

If you are not continously generate data, there is an upper limit for yout data, for instance 250 data-points. In this case I would suggest to use a software- technique (circular Buffer) to store the data and to send them out concurrently.


Hope that helps. Have fun


user_134344396's picture
56 posts

I will most likely only need to capture 500 ms of data every 1-2 seconds. That means I'll have 500-1500 ms extra to send the data.

How big of a circular buffer should I try?

uday's picture
Cypress Employee
569 posts
  • Using CPU to transfer data from ADC to UART will be time consuming process
  • As told in the previous post, it might be difficult to achieve this. For 60ksps, 8 bit samples, Baud required would be 60k X 10 bits = 480 kbps. Theoritically PSoC Creator component supports this Baud. It might be possible to achieve this with the help of DMA. The DMA can be configured to have the ADC_OUTSAMP register as the source and UART TX PTR as the destination. Every EOC can trigger the DMA to intiate this transfer. Since the goal is to sample 2 channels, Amux component(Analog Hardware Mux) has to be used. Switching between the two analog channels can be automated with the help of EOC.
  • Since you intend to measure 2 separate analod channels, in case of Delsig ADC you have to use multisample mode. In this mode the maximum sample rate is about 91 ksps(45 ksps per channel).


jataalfer's picture
2 posts

Hi, I have a similar problem that arises in the forum and let me know if you found a solution.
I'm sampling a signal to 1 ksps and am sending the data via Bluetooth to a speed of 115200bps with TX8_SendData function.
The problem is that I think the buffer is full too fast and the receiver does not work in real time.
I hope you can help with this.

user_119377051's picture
866 posts

Hi jataalfer

Your project belong to PSoC1.

1Kbps is easy to do but depend on rather ADC sampling rate.

Its decided by ADC bit width and data clock.

I don get that you said "receiver does not work in real time"

problem of receiver is depend on it, what use? how?


you have to check Tx empty before TX8_SendData()

user_1377889's picture
9241 posts

Some comments on your source:

It is always advisable to post the complete project (in the right forum) using Designer "File -> Archive Project..."

You do not check your Rx for a character beeing ready.

After switching the AMUX the next 3 ADC-values should be discarted.

There is no buffer I can see that may overrun.



user_14586677's picture
7646 posts

There is an example project using USBFS, described as follows -


This project enumerates USBFS component as a 8-bits, 32kHz, mono USB Audio Device. The audio data is passed to 8-bit DAC using two DMAs. One DMA is integrated in USBFS component used for sending and receiving data to/ from the memory cyclic buffer; the other DMA (VDACoutDMA) moves data from memory buffer to VDAC8.

The synchronization of incoming transfers with internal 32kHz clock is done by the software. It works when cyclic buffer overflows.
When internal 32kHz clock is faster compared to PC transactions, VDACoutDMA  stops for a while to fill the buffer.
When internal 32kHz clock is slower compared to PC transactions, then one USB transfer is skipped.

This project doesn't work with PSoC5 silicon due to the use of DMA Endpoint Memory Management in the USBFS component.


You might consider working with this and modifying the example.


Regards, Dana.

user_78878863's picture
2551 posts

@jataalfer: please don't hijack old threads with new questions - please open a new thread. This will increase you chance of getting a good answer.

Also, note that this is the PSoC3 forum. If you post to a PSoC1 forum, you are also more likely to get a good answer (not all PSoC1 gurus read here...).

Thanks, hli

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