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Toggle GPIO line on I2C address receive | Cypress Semiconductor

Toggle GPIO line on I2C address receive

Summary: 3 Replies, Latest post by danaaknight on 04 Jun 2015 04:14 PM PDT
Verified Answers: 1
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DVDBE's picture
11 posts

 I'm using the CY8C21534 with the I2CHW UM as slave. Capacitive sensors are scanned and when a sensor is active, I set a GPIO line low. The I2C master device detects this falling edge on the GPIO line and starts to read the I2C data from the CY8C21534. When the CY8C21534 receives the address byte, I need to immediatly set the GPIO line back high again. How can I  do that? Where can I generate an interrupt when the address byte is received?

user_14586677's picture
7646 posts

I am not an expert here, but from datasheet -


The I2C resource supports data transfer at a byte-by-byte level. At the end of each address or data transmission/reception, status is reported or a dedicated interrupt may be triggered. Status reporting and interrupt generation is dependent on the direction of data transfer and the condition of the I2C bus as detected by the hardware. Interrupts may be configured to occur on byte-complete, bus-error detection and arbitration loss.

Every I2C transaction consists of a Start, Address, R/W Direction, Data, and a Termination. The I2C resource used for this user module is capable of operating as either an I2C Master or I2C Slave. For either the Master or Slave operation, this user module gives an interrupt based buffered transfer mechanism. Communication is initiated from a foreground function call. At the completion of each byte of the message, an interrupt is triggered and the I2C bus is stalled, the interrupt service routine (ISR) given takes appropriate action on the bus allowing communication to continue, depending on the initialization performed by the user. A slave device which does not acknowledge an address is not interrupted again until the next address is received. Slave devices must respond to each address either by acknowledging or not-acknowledging.

Ignoring differences between a Master and Slave, two general cases exist, that of a receiver and that of a transmitter. For an I2C receiver, an interrupt occurs after the 8th bit of incoming data. At this point a receiving device must decide to acknowledge (ack) or not-acknowledge (nak) the incoming byte whether it is an address or data. The receiving device then writes appropriate control bits to the I2C_SCR register, informing the I2C resource of the ack/nak status. The write to the I2C_SCR register paces data flow on the bus by uninstalling the bus, placing the ack/nak status on the bus and shifting the next data byte in. For the second case of a transmitter, an interrupt occurs after an external receiving device has given an ack or nak. The I2C_SCR may be read to determine the status of this bit.


It looks like the ISR that slave is using has to determine if data or address has been received. Its

at that point where a GPIO could be flipped. Seems to me this would be done in I2CHW_2INT.asm

file, but I do not see where. There are several locations in that file for user code, but its not clear to

me which place is. If I look at the asm file this is where I think you would flip the GPIO,

Lines 424 on -


;@PSoC_UserCode_BODY4@ (Do not change this line.)
; Insert your custom code below this banner
; By replacing the section from here down to the next block
; a user could process I2C addresses differently
                                                                                                                                          ;to this new address by looking at the status bits
    ;inc [rec_cnt]
    mov A, reg[I2CHW_2_DR]
    and F, 0xF9                                                      ;clear Carry (C) AND Zero (Z) in Flag reg
    rrc A                                                            ;carry now holds bit 0 (r/~w) from addr byte
IF (I2CHW_2_AUTO_ADDR_CHECK^1)   ;; for CY8C28X45 chip: skip address comparison and NACK sending stage-hardware will do this for us  if AutoAddressCompare feature is enabled.
                                          ;; The code in this pre-compiler directive will be executed for all chips except CY8C28X45.
    xor A,  I2CHW_2_SLAVE_ADDR                                       ;for an equate
    jnz I2C_Terminate
    or [I2CHW_2_RsrcStatus], I2CHW_ISR_ACTIVE

; User could modify this section to allow the I2C routine
; to respond to multiple addresses, ram addresses, i/o pin
; based addresses, etc.

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Regards, Dana.

DVDBE's picture
11 posts



Thank you very much for the hint.

I added the following code to the section you indicated in "I2CHWInt.asm":

or [Port_1_Data_SHADE], 0x08

mov A, [Port_1_Data_SHADE]

mov reg[PRT1DR], A


and it works; P1[3] goes back high just after the address byte is received.


Best regards,



user_14586677's picture
7646 posts

Glad to hear it worked. As long as the code is inside the allowed

"banner" it won't get wiped out during a clean and build when that

file gets regenerated.


Regards, Dana.

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