Shadow Register Basics | Cypress Semiconductor
Shadow Register Basics
My understanding of shadow registers is a little lacking and I've come up with some questions that I think will help clarify them for me. In the pdf for AN2094, a scenario is given in which the input pin will be permanently latched high.
Why does writing a '1' to P0 permanently set it high?
- Is there an actual voltage being put on the pin?
- Can the input only be set permanently for 'resistive pull up' or 'resistive pull down'?
- I can't see how this could be the case for 'high z'
- Would 'resistive pull up' be in danger of latching high and 'resistive pull down' be in danger of latching low, or would they both be in danger of latching either way?
The other thing that is confusing me is why using a shadow register bypasses this problem? From the example, '1' is written to P0 which causes it to latch permanently. I don't see why performing the following statements differs in results:
The difference that I can see is that one sets PRT0DR via a 'copy' machine instruction while the other does it using an 'or' machine instruction. Would this make a difference in the latching?