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STILL NOISE IN THE SECOND COLUMN (Good) | Cypress Semiconductor


Summary: 1 Reply, Latest post by btk on 09 Jun 2010 06:45 PM PDT
Verified Answers: 0
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user_48311473's picture
71 posts

Thanks about the Enoa parameter. The datasheets states:

ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

But anyway, I introduce  a sinusoid into a PGA follower  (Gain=1) and apart  I monitories the input and output in the First column and I get the image 1, obtaining the expected.

Input=Output (Port 0_3)

(Vsin input= 500Hz 1Vpp and 1Voffset)

When I did the same in the second row I got a noisy sinusoid  output.  The output is equal to the input but the noise is much higher than the specifications told in the datasheet, so I still thinking my part is damaged.

Image 3 shows the add noise is around 800KHz and 1MHz.

What do you think about it?

Is damaged my part?

By the way, I have a RC filter in my Port 0_5  board outout.

Could it produce the noise?


btk's picture
Cypress Employee
3 posts


Are you by any chance using a CY3214 board? If so, what revision is it?

This board has a capacitor on the P0.5 pin that is used for CapSense. If you output an analog signal on P0.5, your output will not be as expected because the analog output buffers in the PSoC device cannot drive very large capacitances. The capacitor on the board is around 10 nF and the analog output buffer can drive around 200 pF, max. So, this is why you are seeing a signal on P0.5 that is so unexpected.

I would either try the output on P0.3 or try removing capacitor C7 from your board.

Best regards,

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