SAR6 Sample Clock | Cypress Semiconductor
SAR6 Sample Clock
My project consists in programming the PSoC as a signal adquisitor using the different types of ADCs in order to see the differences between them.
Now I am trying to use the SAR6 ADC but I don't fully understand how it works when it get the samples.
When I read the datasheet and the API functions I understand that the sample is taken when I call the SAR6_cGetSample(), and it takes some microseconds to convert the sample. Then, how does the Analog Column Clock influence in the Sample Rate? It seems that the Sample Rate would be related to the code where I have the SAR6_cGetSample() function instead of the Analog Column Clock.
Another doubt is why some tables of the datasheet say that the Conversion Time is 20 microseconds with the condition of a CPU of 12 MHz and fclock of 250 kHz, if then the datasheet says that this time is six times the period of the sample clock. Is it a variable parameter or not?
And finally, understanding that fclock mentioned in the tables of the datasheet is the same as sample clock (phi1 and phi2), why is it limited to 333 kHz if it depends on the Analog Column Clock? It would be some MHz, couldn't it?
What I am misunderstanding?