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PWM output incorrect | Cypress Semiconductor

PWM output incorrect

Summary: 1 Reply, Latest post by graa on 03 Mar 2011 02:36 PM PST
Verified Answers: 0
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koushi's picture
5 posts



I am trying to get a 1KHz output from a PWM.  I am using a 8 bit PWM with the following configurations.


Clock - VC2 (VC1 divider = 16; VC2 divider = 15)

Period = 99

Pulsewidth = 50


With VC2 clock at 100KHz, with PWM period of 99, the output should be 1KHz.  But I am getting an output near 240KHz from the PWM.  Can someone point me what could be the mistake?




graa's picture
Cypress Employee
223 posts

From the data you have provided the only possible problem in your design could be the ClockSync parameter of the PWM.  Have you set this to "Use SysClk Direct"?  When the ClockSync parameter is set to "Use SysClk Direct", it overrides the clock parameter and connects the 24MHz clock to the PWM.  With a 24MHz clock and a period of 99, the output would be 240KHz.  Change the ClockSync to "SyncToSysClk" and that should fix your problem.


Best Regards,


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