PSOC1 and CyFi artaflex problem | Cypress Semiconductor
PSOC1 and CyFi artaflex problem
I know that this isn't the first time this topic is talked about here. but I did everything that was written in the forums and application notes and still can't make it work.
I have a CY3210-PsocEVAL1 kit and an artaflex awp24s Cyfi module, working on the Psoc Designer 5.1.
Because the artaflex requires a 3.3v operation voltage I'm working on the Psoc with an external voltage source and using the built in VRM (U3) on the Psoc to supply the board and artaflex with a 3.3v Vcc. The CPU_clock is set to SYSCLK/2=12Mhz, VC1=SYSCLK/2 (12Mhz), VC2=VC1/3 (4Mhz).
In the designer I used the CYFISNP module and selected the HUB with GPIO IRQ. I connected all the required ports and VC2 (4Mhz) as the clock to the CYFISNP module and from the ports to the artaflex module.
In all the tutorials and code examples I have seen all start with a loop to start the CYFISNP protocol:
"do stuff, or wait......"
and only when this loop expires, that means the CYFISNP has been successfully initialized they continue in all the other routines like Binding, RX pooling etc.
My problem is in that loop for initializing the CYFISNP protocol, when I run this command (CYFISNP_Start()) even once it doesn't return any value, it's just get stuck in that command and the Psoc freezes. When I check the nSS, MISO, MOSI, SCK lines with an oscilloscope i see an activity for some time, about 24 clock cycles (SCK), about the same MOSI write activity and nSS, and 3 MISO activities, one after 2 SCK cycles and 2 some where in the end of the 24 clock cycles i mentioned.
What am i doing wrong? it's supposed to be a simple and friendly protocol.
Please any help would be appreciated.