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PSoC Fundamentals: enabling - disabling Variable Clocks (VC1, VC2 and VC3) | Cypress Semiconductor

PSoC Fundamentals: enabling - disabling Variable Clocks (VC1, VC2 and VC3)

Summary: 1 Reply, Latest post by graaja on 01 Jun 2010 08:24 PM PDT
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delmasli's picture
2 posts

I'm reading Application Note of “ PSoC Fundamentals: Clocks September 24, 2007 Document No. 001-32200- Rev. ** - 1 -   AN32200 “

(Link: )

At the page 3 (end of “ Variable Clock 3 (VC3) section) it is written that “When not used for any purpose, VC3 must be set so that it has the lowest possible frequency. This uses less power in the PSoC. The same principle is also true of VC1 and VC2.”

1-) As far as I understand If we don’t use VC3 in our system (firmware) it must be set to the lowest freq as it is possible. Such as for VC3, source will be VC2 and VC3 divider will be 256?

2-) Just for my curiosity: There isn't  “N/A source input “ selection for VC3 (and also for others) in the Global Resource Screen of PsoC Designer Program. Is it possible to select no-input (I mean disabling) by modifing OSC_CR2 , OSC_CR3 or OSC_CR4 registers (also for other variable clocks: VC1 and VC2) without getting compiler or hardware incompatiblity error? Or for every cases (even if we need or don’t need VC1, VC2 or VC3), do these source inputs have to be defined for Variable Clocks ?


Kind Regards

user_11685479's picture
41 posts


1. Yes.  You are correct.  The lowest possible setting for VC3 would be VC2 as source and a divider of 256.  In case VC2 is not used, set its divider to 16.

2. No.  There is no option to disable the clock dividers.

Best Regards,
PSoC Hacker

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