No FEC in the CyFi? | Cypress Semiconductor
No FEC in the CyFi?
From the scarce information provided about the Phy of CY3271 modem I could not find any mention to a forward error correction (FEC) scheme, which is almost always used in digital wireless schemes, e.g.convolutional encoding -> Interleaver -> Deinterleaver -> Viterbi decoding. Is it the case that the Phy only relies on the spreading gain provided by the DSSS scheme and power level control to overcome the inevitable channel errors?
I understand that the simpler the Phy (and the upper level protocol) the more power efficient the chip will be, also it might be the case that the packets are short (5 bytes maximum?) so for the same SNR they are less prone to be in error than a longer packet. Anyway, this looks like an interesting chip/kit.