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Mismatching Noise Margin for CY8C21334 | Cypress Semiconductor

Mismatching Noise Margin for CY8C21334

Summary: 1 Reply, Latest post by btk on 09 Jun 2010 07:05 PM PDT
Verified Answers: 0
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Karthi's picture
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all other Devices specifications are Vdd*0.7 for VOH(min). But CY8C21334 having Vdd-1, Vil = 0.8V, Vol = 0.75. if operate Vdd = 3.3V, Noise margin for logic High = -0.01. And a one more device same operating voltage Specifications are Vih = 3V, Vil = 0.3V, Voh = Vdd*0.65( 2.145V) and Vol = 0.6V this is totally not matched with CY8C21334. these margin Values are logic H = -0.7 and logic L = -0.45. Please give the solution for matching all other devices.

btk's picture
Cypress Employee
3 posts

Hi Karthi,

The Vih = 3V(min) and Vil = 0.3V(max) specs for the device you are using appear to be not very good. These seem to be pretty high and low, respectively for CMOS device logic levels.

But, you can likely make it work just fine. The Voh=Vdd-1 and Vol=0.75 specs for PSOC devices are worst case and assume quite a bit of load current. You will notice in the datasheets that those specs hold true for currents on the order of 10mA or 25 mA. So, if the output current on the pins is very low, then you can expect much better Voh and Vol numbers. I would try taking a look at AN2405 "Power Management - PSoC IO Power Structure - Determining VOH and VOL at Partial Load" The link to it is here.

Based on Vdd, you can calculate the resistances in your device. You can then figure out how much output current is required, and this will allow you to solve your max/min Voh and Vol values.

Best regards,

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