Mismatching Noise Margin for CY8C21334 | Cypress Semiconductor
Mismatching Noise Margin for CY8C21334
all other Devices specifications are Vdd*0.7 for VOH(min). But CY8C21334 having Vdd-1, Vil = 0.8V, Vol = 0.75. if operate Vdd = 3.3V, Noise margin for logic High = -0.01. And a one more device same operating voltage Specifications are Vih = 3V, Vil = 0.3V, Voh = Vdd*0.65( 2.145V) and Vol = 0.6V this is totally not matched with CY8C21334. these margin Values are logic H = -0.7 and logic L = -0.45. Please give the solution for matching all other devices.