GPIO Die Layout Problem ? | Cypress Semiconductor
GPIO Die Layout Problem ?
I am using 29666, 48 TSSOP, in a jig with fairly good bypassing, bulk and ceramic.
External 24 Mhz clock to P1(4). Square, fed thru 100 ohm to minimize overshoot, which is 800 mV.
The adjacent pins, P1(2), P1(6), are configured as STD CPU, pulldown.
I read the PRT1DR register and consistantly get a return of "1" for P1(6), even though
nothing is connected to pin, and bit confirmed to have been written as a "0" into register.
Examining all pins in port with fast scope, only on P1(6) do I see ~ 1.5V of the external
clock coupled into the pin from the external clk, P1(4). The clk artifact has overshoot
reaching 2 V, and baseline high level of 800 mV. No other pin in port, all configed as
STDCPU with pulldown exhibits this.
5 pF stray at 24 Mhz is ~ 1.3K, Min pulldown = 4K, so 5V results in ~ 1.2V. But
again no other port pins show anywhere near the coupling that P1(6) does.
Scope probes calibrated by high speed cal routine provided by scope.
Looks like a die layout issue ?