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GPIO Die Layout Problem ? | Cypress Semiconductor

GPIO Die Layout Problem ?

Summary: 2 Replies, Latest post by danaaknight on 24 Jun 2012 06:41 PM PDT
Verified Answers: 0
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user_14586677's picture
7646 posts

I am using 29666, 48 TSSOP, in a jig with fairly good bypassing, bulk and ceramic.

External 24 Mhz clock to P1(4). Square, fed thru 100 ohm to minimize overshoot, which is 800 mV.

The adjacent pins, P1(2), P1(6), are configured as STD CPU, pulldown.


I read the PRT1DR register and consistantly get a return of "1" for P1(6), even though

nothing is connected to pin, and bit confirmed to have been written as a "0" into register.

Examining all pins in port with fast scope, only on P1(6) do I see ~ 1.5V of the external

clock coupled into the pin from the external clk, P1(4). The clk artifact has overshoot

reaching 2 V, and baseline high level of 800 mV. No other pin in port, all configed as

STDCPU with pulldown exhibits this.


5 pF stray at 24 Mhz is ~ 1.3K, Min pulldown = 4K, so 5V results in ~ 1.2V. But

again no other port pins show anywhere near the coupling that P1(6) does.


Scope probes calibrated by high speed cal routine provided by scope.


Looks like a die layout issue ?


Regards, Dana.

user_1377889's picture
9296 posts

Hi Dana,

can there be the possibility that you "burned" that pin during some tests? I have a similar situation with my PSoC Pod where I killes a pin of port 1.


PS: Congratulations, you overtook me in posts!

user_14586677's picture
7646 posts

Getting back to basics, the simulation tells it all.

But still interesting one pin seems to have more sensitivity than another.

Rergards, Dana.

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