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DAC6 | Cypress Semiconductor


Summary: 2 Replies, Latest post by mmoron21 on 21 May 2010 10:57 AM PDT
Verified Answers: 0
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user_48311473's picture
71 posts

I input a 6bits_code_min=0dec or 6b_code_max=62dec value into the DAC6 by means WriteStall API and I get unexpected Voutput value.

Theoretically the DAC6 datasheets told us:


Taking into account my reference Vdd/2+/-BandGap I must to have:



Instead of this I obtain a more or less a  Vout=3.7 V  and after that the value is going down until reach

aproximattely 2.5V. I put the analog outputs in High Z.

The C code is simple:



"PSoCAPI.h" // PSoC API definitions for all User Modules




DAC_MAX (62) // Define max DAC value as 62



char bDACValue = DAC_MAX; // Variable for the DAC value


char j; // Variable for an index







main() // Start DAC6 in HIGH power mode



while(1) // Repeat forever



//for(j=0; j<62; j++){



for(i = 0xFF; i != 0; i--); // Delay loop

for(i = 0xFF; i != 0; i--); // Delay loop


for(i = 0xFF; i != 0; i--); // Delay loop


}/*while*/ /*main*/

Anyone could tell me what's going on?  Thanks


graa's picture
Cypress Employee
223 posts

Some points to check:

1. What is the column clock setting for the DAC?  Depending on the power you operate, there is a maximum column clock limitation.  If the column clock is more than the limit, then the DAC output will not be as expected.

2. Is the DAC set to signed or unsigned?  If set to unsigned, you will get REFLO at the output, ie, 1.3V.  For a value of 62, you should get REFHI which is 3.8V

user_48311473's picture
71 posts


I'm using a 136KHz frecuency column clock. Much lower than the 3.2MHz  let it with high Power

use modele way.

The DAC is signed?

The input data is OffsetBinary. I shoudl to obtain following the formula a values between 2,6V and 3,9V.

I got a ramp, but is not between the values I hope.


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