Planning TCXO with Clipped Sine Wave for Programmable Clocks – Check Conditions Here! | Cypress Semiconductor
Planning TCXO with Clipped Sine Wave for Programmable Clocks – Check Conditions Here!
The clipped sine wave is not a problem. If you turn off all of the load capacitors in the programmable clock devices, this will reduce the capacitance load on the XIN Pin to 12pF for the CY22392, CY22393/4/5, CY22381 and 15.6pF for CY22050, CY22150, CY22801 that can be programmed using CyClocksRT. You will then need a clipped sinewave of +/- 1 Volt peak to peak on the input side or XIN side of an AC coupling capacitor connected back to the output of the TCXO.
There are no specific TCXO recommendations, but from an application point of view, Cypress clock generators and programming software are set up to handle a driven external reference. The easiest recommendation is to simply purchase a low cost 3 by 5 mm TCXO and drive this into your chosen part as the clock reference.
For the external reference, as long as the input reference signal goes through [(VDD/2) +/- 1V)], it should be fine as the phase detector compares the Reference and Feedback signal at the rising edges at VDD/2 level. So only going through VDD/2 should be sufficient, the added “+/-1V” on top of it is for the noise margin.