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Increased Loading Effects on Programmable Clocks! | Cypress Semiconductor

Increased Loading Effects on Programmable Clocks!

Summary: 0 Replies, Latest post by Stub for 2594006 on 23 Dec 2011 07:44 AM PST
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Stub for 2594006's picture
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Many of you may think of going beyond the datasheet maximum specification of Capacitive Loading.

Generally it is possible to drive two loads from one pin; however, it is good to be cautious.

1. With Increased loading, two loads will double the capacitance loading. Maximum loading is 15pF specified in datasheets. The total device loading becomes ~30pF, which is enough to noticeably affect the edge rate.

2. Signal integrity: With two loads, layout is important. If the two loads are very close together, then it's possible to have one trace which then branches very close to the loads. However, this is not common. More commonly it is recommended branching very close to the output of the programmable clock. Then have a series resistor for each branch, located close to the branch. The resistor values will be different than when terminating a single load. Simulations are always recommended.

3. Total loading for the chip: Double loading every output on a chip has a cumulative effect on the chip and is generally discouraged. It's good if the double load is only on a single output. It's best if the other outputs are not used. If they are used, especially for different frequencies, then the heavy loading on this output may increase jitter in the other outputs.

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