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Frequency and Jitter Dependency in Programmable Clocks | Cypress Semiconductor

Frequency and Jitter Dependency in Programmable Clocks

Summary: 0 Replies, Latest post by Stub for 2594006 on 25 Sep 2011 04:27 PM PDT
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Jitter in programmable clocks is dependent upon the configuration for your application that is determined by the frequencies selected for the outputs with respect to the reference.


A higher VCO frequency will always provide you better jitter performance that should be kept in mind always when we configure our programmable clocks. Lower frequencies generally have higher long term jitter because there is a larger chance of variation with the longer period lengths. A 1us period for a 1MHz signal with 1% of jitter can vary up to 10ns, a 10ns period for a 100MHz signal with 1% of jitter can vary up to 100ps.

With a lower frequency, if your VCO is running slower, it increases jitter, or if you are using a larger divider value, it also increases the jitter. The larger divider value can increase jitter because you have that much more logic and circuitry to go through, and each gate can add a little more variation which will accumulate and show up in the final output frequency.

The typical peak-peak period jitter value totally depends on the configuration of the device, number of outputs in use, output loading. Same frequency on all outputs and equal loading will have smaller jitter numbers. Jitter can be lowered by using the least number of outputs. Another parameter is the Q value. Using smaller Q values will also help decrease the peak-peak jitter. Different frequency combinations will yield different P and Q values, and you generally want the lowest P and Q values possible.

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