CY22393 P Q dividers and CyClocksRT | Cypress Semiconductor
CY22393 P Q dividers and CyClocksRT
We are working on a new desing using CY22393 programmable PLL to generates a synchronous clock from another.
We have calculated P and Q dividers and post div values and would like to check that they are compliant with your internal component constraints using your CYClocksRT software but there is no way to enter manualy que P Q and post div values in this software.
The sofware only works from enterred frequencies values, but it does not calculates the same P and Q values has we have determined and the obtained output frequency is less accurate than the one using our calculted values.
For example our input frequency is 27 * (1000 / 1001) MHz so approximatively 26,973027 MHz
We want to output a precise 9.6 MHz frequency and we have determined that it can be precisely generated using the following values :
post div = 25
Do these values match our component internal constraints ? There is no precision in the datasheet about these constraints, just a instructions to use CyClocksRT software.
But the sofware doesn't the calculated the values we want to use the obtained frequency is not as exact as what we can get.
In our example the software computes the following values :
post div = 29
Frequency output = : 9,60000590 MHz frequency
Thank your for your support,