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Using SCB Module as SPI NOR Flash Controller | Cypress Semiconductor

Using SCB Module as SPI NOR Flash Controller

Summary: 5 Replies, Latest post by PRKU on 25 Oct 2017 10:01 PM PDT
Verified Answers: 0
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Ted Mawson's picture
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35 posts

My design - which is built at qty 25 prototype stage - connects a Cypress (formerly Spansion) S25FL512S NOR Flash memory IC with a CYBLE-222014-01 module using SPI.  I've set up an SCB module and I'm trying to follow the instructions in the attached pdf given to me by a Cypress FAE.  I renamed my SCB module to "SPIM" and my hardware-provided CS pin is called "NOR_CS" because I have a second device on the SPI bus that's using the dedicated SPIM:ss0_m pin for an accelerometer.  I have 2 questions, one hardware and 1 software:

Hardware: The FAE advises that, can I force the SPIM:ss0_m pin dedicated to the accelerometer to stay high while I run the SPI bus to access the NOR but I'm not sure of the best way to do this so I'm looking for a recommendation on the best way.  Maybe I should have dedicated a pullup resistor for this but that pin's also shared with SWDIO so I'd rather not if at all possible.

Software: In following the instructions, I found problems in slld_hal_example.c (zipped copy attached), it seems that the code was written for an earlier SPI module so not all the API commands match.  In the file you'll see pairs of lines like this...

//            SPIM_ReadRxData(); // drop a dummy byte               // TM OLD LINE
            SPIM_SpiUartReadRxData(); // drop a dummy byte

Where the first line is the old original line and the second is my 'translation'.  However, there's a line that I can't find an obvious comparison to - now lines 54 and 55 in my file:

//    while (0u == (SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE))       // TM OLD LINE
    while (0u == (SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE))

That same command appears at line 95.  Clearly, all that's needed is to check the status of the SPI bus to make sure that the previously requested transfer has finished but there's no "ReadTxStatus()" API in the list for the SCM module.  Again, I'm looking for advice on how to replace this line.

If anyone has done the interface I'm attempting and wants to steer me in a different direction, I'm willing to listen - hopefully what will end up in this thread is a solution for all who follow in my footsteps.

Ted Mawson's picture
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35 posts

I've been looking at this some more today:

Hardware: I found this thread http://www.cypress.com/forum/proc-ble/proc-ble-spi-single-master-multipl... the forum.  It matches my scenario pretty well with a NOR Flash memory and an accelerometer on the same SPI bus; fortunately, as far as I can tell, the accelerometer and the flash will coexist on the same SPI bus signals and I have been able to specify 0 chip selects and then set up the pins I originally intended to use as the ACC_CS and NOR_CS as suggested in that other thread.  The accelerometer chip (LIS2DH) also has a 3x32 FIFO buffers for the X,Y,Z channels and given that I'll be reading the accelerometer 10 times per second, that means I can store 3 seconds of data on the accelerometer IC which gives me enough time to perform sector erase while not accessing the accelerometer - the max time it takes to perform a sector erase is 2600 mS - which would seem to overcome this issue that other poster had.

Software: The unanswered question I have is that the command to check that the SPI transfer has been completed included in the example in the uploaded the zip file isn't recognized by the SCB code that's generated by PSoC Creator, specifically...

/* Wait for the end of the transfer. Monitor the SPI_DONE status */
while (0u == (SPIM_ReadTxStatus() & SPIM_STS_SPI_DONE)) <=== this function is not recognized
{
}

Please can you give me guidance on how best to replace that test. Thanks,

Ted

user_1377889's picture
User
10803 posts

Your function SPIM_ReadTxStatus() is not made for the SCB implementation, it is an API for the SPI Master 2.5 component which is UDB-based.

Easiest will be to check for the number of bytes received in the master's Rx buffer which must be the same as the number of bytes sent by the master when transfer is completed.

 

Bob

Ted Mawson's picture
User
35 posts

Bob,

Even though the commands I've tweaked in the code now are recognized, there are a bunch of registers that are referenced in the .h files that could well be different between UDB and SCB implementation - I'm worried it will not only not work, it may screw up my NOR Flash memory IC.  Do you think I'd be better trying to base my code on an SCB-based example such as the SCB_SpiMaster01 for PSoC 4200?

Thanks,

Ted

user_1377889's picture
User
10803 posts

The SCB is kind of a jack of all trades device. Thus why the .h file is more than a bit (byte?) voluminous. A #define for any register does not yet access that register, this is done (or in this case mostly not done) in the corresponding .c file. Keep in mind that the .h and .c files for the components (SPI) get generated automatically. So there will be no danger for your external memory.

By the way: Cypress offers FRAM chips which are quite smaller, but do not need erasing or precautions for power loss.

 

Bob

PRKU's picture
Cypress Employee
32 posts

test post

 

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