Trying to understand clocks | Cypress Semiconductor
Trying to understand clocks
I made a very simple test jig , where the system clock is set to 48MHz, no dividers. I am simply toggling a pin.
/* Place your initialization/startup code here (e.g. MyInst_Start()) */
/* CyGlobalIntEnable; */ /* Uncomment this line to enable global interrupts. */
/* Place your application code here. */
but I am not seeing the pin toggle at nearly the rate I would expect given the system clock speed. Frequency of the output is 350kHz, so it is 48MHz/350kHz = 137 off from 48MHz. I have a hard time believing that there are so many cycles per instruction. Rather, I am thinking something is not configured quite right in my project. What could it be?
Also, why is there a question mark under Desired for Sysclk?