Reduce KitProg's 4.5MHz clock speed | Cypress Semiconductor
Reduce KitProg's 4.5MHz clock speed
I have the CY8KIT-042-BLE with onboard kitProg, I am trying to debug an CYBLE-012011-00 that I wired to J11.
Communication fails almost all the time, wires are certainly too long (40mm). It's sometimes recognized but the looses the communication.
By default PSoC programmer and PSoC Creator have SWD set to 1.6MHz. I reduced the second to 0.2MHz but setting doesn't seem accessible for the first. Still doesn't work.
Then I probe SWDCLK: it's bursting at 4.5MHz !!! no matter the setting, it's just trying to communicate at 4.5MHz, how can I reduce this?