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Reduce KitProg's 4.5MHz clock speed | Cypress Semiconductor

Reduce KitProg's 4.5MHz clock speed

Summary: 2 Replies, Latest post by jerome on 21 Nov 2016 02:20 AM PST
Verified Answers: 0
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jerome's picture
8 posts


I have the CY8KIT-042-BLE with onboard kitProg, I am trying to debug an CYBLE-012011-00 that I wired to J11.

Communication fails almost all the time, wires are certainly too long (40mm). It's sometimes recognized but the looses the communication.

By default PSoC programmer and PSoC Creator have SWD set to 1.6MHz. I reduced the second to 0.2MHz but setting doesn't seem accessible for the first. Still doesn't work.

Then I probe SWDCLK: it's bursting at 4.5MHz !!! no matter the setting, it's just trying to communicate at 4.5MHz, how can I reduce this?

Thank you,


Anjana Muralidharan's picture
Cypress Employee
160 posts

Hi Jerome,

Please avoid using long wires for SWD programming. Because it may effect the clock speed. Use small wires as possible.

Also if you select low frequency, then it will set for low frequency , it won't be showing 4.5MHz. Please check whether the programmer settings are correct.




jerome's picture
8 posts

Thank you Anjana for your reply, my wires are not long.
Where do you select "low frequency" ?
What are the "correct" settings?
Thank you.

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