Calculate SW_Tx_UART BaudRate error | Cypress Semiconductor
Calculate SW_Tx_UART BaudRate error
I am very new to Microcontroller and especially Cypress programming and have therefore been looking at the code examples. I am currently trying to understand the function of the SW_Tx_UART Component.
First of all I would like to know, how it is possible to change the clock the component is using? And how do I know which it is currently using?
For documentation sake I would now like to calculate the expected baud rate error. The following formula is given in the SW_Tx_UART- Datasheet:
Divider = (int) (CPU_CLK+(BaudRate/2))/BaudRate
%err = (BaudRate - CPU_CLK/ Divider)*100% + CPU_CLK_Accuracy
But which values do I need to enter here? Is the CPU-CLK the same as the SYSCLK? I also don't know in which units the values have to be given since I don't seem to be able to fully understand the relationship between clock frequency and baud rate.
For example if the used clock is runnig at 48000000Hz (48MHz) and a I set a Baudrate of 115200 Bd that would give me a divider of 417.166 (ignoring the units). The result seems a bit high I think...
Any help in understanding the relations of clock and baudrate is much appreciated.