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PCB layout and Guidelines for CY14B101P SOIC16 | Cypress Semiconductor

PCB layout and Guidelines for CY14B101P SOIC16

Summary: 1 Reply, Latest post by zsk on 07 Feb 2013 12:12 PM PST
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I'm having  trouble to find some pcb layout and guidelines for CY14B101P. As you guys know, it's packaged as SOIC16.

So, my doubt: Does anybody know where i can find the pcb guidelines for CY14B101P or for SOIC16???

Thx so much!


Fávero Santos

zsk's picture
Cypress Employee
27 posts

Hi Favore,

We don't have any ready to share PCB layout design guidelines for specifically for the CY14B101P in SOIC 16 package option. We consider that CY14B101P is a standard SPI memory which operates at maximum 40 MHz SPI frequency. If the layout designer follows the defacto PCB layout standard practices, this will be sufficient to achieve good SI without any challenge. However this doesn't apply for  the RTC circuitry as this requires special attention to get the best clock accuracy. We have published an application note (AN61546 which discusses about RTC best design practices in details including PCB layout for all nvSRAMs including CY14B101P.

Hope this helps.

Thanks and Regards,

Shivendra Singh

Cypress Semiconductor


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