NvSRAM RWI Inhibit vs WE line | Cypress Semiconductor
NvSRAM RWI Inhibit vs WE line
I have a Question about the RWI Inhibit in the Datasheet. Is that an internal Inhibit, or is it controlled by the WE what is the relationship? If WE is not up the first 20 ms, what is the probability of having corrupted data. Can you elaborate more on that relatinoship.