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NvSRAM RWI Inhibit vs WE line | Cypress

NvSRAM RWI Inhibit vs WE line

Summary: 1 Reply, Latest post by psr on 19 May 2011 03:28 AM PDT
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Maged's picture
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I have a Question about the RWI Inhibit in the Datasheet.   Is that an internal Inhibit, or is it  controlled by the WE what is the relationship?  If WE is not up the first 20 ms, what is the probability of having corrupted data.   Can you elaborate more on that relatinoship.  

psr
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Hi Maged,

RWI is an internal inhibit. It is not controlled by WE/. During RWI, condition of WE/ pin or any other control pin has no relevance. And hence, data cannot be corrupted by any means during RWI. Only at the end of the RWI, the WE/ condition will matter. Therefore, we suggest a pull up on WE/ pin to ensure that unwanted writes do not happen after RWI is enabled (and the controller is still booting up).

Thanks

Ravi

Note: To state the obvious, the pull up helps only if the controller IO is in tristate when nvSRAM has completed boot up - at end of tHRECALL - and not if it is in LOW state. Also, you can see that instead of WE/ you can ensure CE/ is HIGH which would have the same effect since any unintended write can happen only if both CE/ and WE/ see a LOW condition at the pins.

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