NVSRAM CY14B104NA Single Event Upset - Multi Bit Upset mitigation query | Cypress Semiconductor
NVSRAM CY14B104NA Single Event Upset - Multi Bit Upset mitigation query
A popular on-line encyclopedia page informed me that memory device manufacturers protect against MBUs affecting single words by having the cells organised so that physically adjacent cells are not part of a single word of memory. Thus a MBU appears as multiple Single Bit Upsets in different words in RAM. The article did not detail whether this was only a practice associated with ECC memory. Using non-ECC memory, I plan to use three copies of "SEU protected" data, and want to align the blocks to ensure that an MBU does not identically affect two of the copies. Where can I learn about the memory layout of the particular part I am using - CY14B104NA - so that I can align the blocks with care and avoid MBUs causing an identical corruption in two of my copies?