Ganging nvSRAMs, vswitch threshold tolerance | Cypress Semiconductor
Ganging nvSRAMs, vswitch threshold tolerance
I am working on a design using five STK14CA8 devices. These are ganged to make up a 32bit bus plus a 4th byte for syndrome bits - so 40 bits wide total
The design uses pullups on WE CE OE and HSB (10K)
HSB is ganged between all devices, pulled up, and routed to my system controller
There is one VCAP, also ganged to the 5 devices
The value of the capacitor (VCAP) is 5 times larger to accomodate for the fact that there are 5 devices
Here is my problem:
I have 5 samples (out of hundreds produced) where one of the 5 chips (usually lane 0) gets corrupted in the field. It seems that the entire device is in a random state. Reloading corrects the issue, and I can't reproduce the problem on any "failed" board. Customers want to know why it failed.
1. If you gang the devices, what will happen if the Vswitch is slightly different from device to device ? Cap discharge is exponential, and if you switch in a device later, after VCAP starts discharging, won't that upset the auto store because it changes the slope of the discharge radically ? Why is there no typical, min and max for vswitch value ? They can't possibly all be the same across all devices produced can they ?
2.How much time passes from the crossing of vswtich to the inhibit of reads and writes ? Can this truly be zero as the datasheet implys ?
3. Why is there no mention of ganging devices in the datasheet - it seems like you CAN NOT DO THIS, at least reliabily. Any opinions there ? (one member says yes you can - but why do you think that ?)
4. It also seems strange that Cypress took off the mention of ganged HSB in their last rev. Is that because you can't do it ?