CY14B256Q2A access methodology problem | Cypress Semiconductors
CY14B256Q2A access methodology problem
I'm running linux on an MPC8308, trying to access a CY14B256Q2A SPI nvSRM and I'm having dificulties. To avoid having to write my own driver, I'm utilizing an existing Freescale driver for the SPI controller in the 8308 (spi_fsl_spi), and an existing interface driver that sits on top of that (spidev specifically if it matters) and I'm unable to even read the status register of the nvSRAM. I'm pretty sure the problem is in the way these two drivers work but I want to confirm it with you since the datasheet for the nvSRAM isn't explicit either way.
To read the status register the device needs to have CS asserted, SPICLK started, and 0x5 clocked onto MOSI. On the first clock following the read status reg command the MSB of the status register gets clocked out on MISO. My question is, what happens if the clock stops for a period of time between the LSB of the commnd and the MSB of the result? I've scoped the signals and what I see is eight clock pulses with the read status reg command, then clock goes silent for about 20msec and then starts back up (CS is held low the entire time), but it appears no data is clocked out of the nvSRAM when the clock starts back up. Does the part require that clock be continuous for the entire transaction?
The fact that burst reads are possible as long as CS is held low implies that the clock can start and stop without impacting the part, but it's not totally clear.