CY14B101NA-ZS25XIT Verilog Modeling Behavior For BHE\ and BLE\ | Cypress Semiconductor
CY14B101NA-ZS25XIT Verilog Modeling Behavior For BHE\ and BLE\
I am interfacing an FPGA with a CY14B101NA-ZS25XIT (x16 NVSRAM). During RTL simulations using BHE\ and BLE\ controlled sram writes, unwritten data is getting corrupted with "z's". For example, I want to write bits DQ15-DQ8 but leave bits DQ7-DQ0 untouched. I use a BHE\ controlled sram write, the high byte gets written to the value I want, however, the lower byte gets corrupted with "z's".
Is this the behavior of the CY14B101NA for byte mode writes?
I was under the impression that bye mode writes would only write the byte selected and leave the other byte alone.
Do I need to read the sram word, modify the byte I want to write, and rewrite the entire word back?
Is this a model issue?
Any feedback would be greatly appreciated to we may find another solution that does meet our requirement. Below is a snippet of verilog code that does the supposed data corruption.
always@( CE_bar or WE_bar or OE_bar or Address or dataIO )
if ((CE_bar==1'b0) && (WE_bar==1'b0)) // Write in progress!
Address1 <= Address;
Address2 <= Address1;
dataIO1[15:8] <= (!BHE_bar) ? dataIO[15:8] : 8'bz ;
dataIO1[7:0] <= (!BLE_bar) ? dataIO[7:0] : 8'bz ;
temp_array0[Address1] <= dataIO1[15:0] ;