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FPGA VHDL interface to S34ML04G1 | Cypress Semiconductor

FPGA VHDL interface to S34ML04G1

Summary: 2 Replies, Latest post by ejfield_2052366 on 23 Nov 2016 01:16 AM PST
Verified Answers: 0
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ejfield_2052366's picture
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2 posts

I'm trying to interface the above device to an FPGA, in x16 mode.  Firstly I'm confused about the address.  IF the device is 512MByte, that should be 29 address bits, but there are 30 (0-29) in the Address cycle map.  I assume this must be for the "Spare area" in each page.  But If I just want to read/write pages of 1024 words, can I ignore one address bit (set it to zero)?  My guess is that I dont use A10.

An example of a VHDL interface would be nice!

regards

Ed

Krishna GSNS's picture
Cypress Employee
48 posts

Hi,

We do not have any reference examples for VHDL interface. We have VHDL model files which can be downloaded form the link given below:

http://www.cypress.com/verilog/s34ml04g1x16-verilog

The address map for x16 mode is provide in the page 11 of the datasheet. Please refer and let us know if you need any clarifications.

Thanks.

 

ejfield_2052366's picture
User
2 posts

Yes, I can read a datasheet thanks.  But it doesn't answer my original question.  I'm designing a simple interface which will read/write pages of 1024 words, sequentially.  How do I map the blocks of data into the address map?

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