Sample/Track & Hold problem | Cypress Semiconductor
Sample/Track & Hold problem
Did peak detector on the component subject. We must remember the amplitude of the square pulse duration > 10us.
The component has configured as follows.
- "Sample & Hold"
- "Falling edge"
Synchronized pulse from the Pulse Converter component, 2us, who was started by digital sygnal under investigation immediately.
On output of Sample & Hold I was see clear 0!
P.S. In main.c component was started, not forgot to do this...