I2CHW - SDA line low problem - detection and solution | Cypress Semiconductor
I2CHW - SDA line low problem - detection and solution
In one of our appllications we're using the I2CHW module (configured as "master only"). We're using it to read/write an EEprom and an I/O expander.
Sometimes, due to a power failure, the main processor resets. Sometimes after that the I/O expander or the EEprom keeps the SDA line low.
Now an I2C slave is holding the SDA line low and our main processor won't startup after its reset because it couldn't finish an I2C transfer. How do you detect something like this and how do you solve this?
On a wiki page i found this:
"There are a couple ways to recover from this scenario.
Option 1: For devices that mux the SCL/SDA pins with GPIO, the easiest thing is to configure the pins for GPIO operation and toggle SCL until the slave releases SDA. At this point you should be able to resume normal operation.
Option 2: Many devices don't mux SCL/SDA with GPIO since the I2C I/O cells are often special open drain cells. A workaround has been reported to work even on these devices. By configuring the I2C for "free data format" and then reading a byte the I2C will immediately start sending clocks to input data (rather than trying to send an address). This can be used to free up the bus."
For our application option 1 could be the answer. So we've written a solution and tested in our application. For us this works right now and doesn't give any problem.
You can find it in the attachment.
The question are:
- Do you see something what's wrong or possible go wrong while running?
- Are there better solutions? Faster/cleaner code or ....