CY8C21x34 Family - UART not working properly with CSD | Cypress Semiconductor
CY8C21x34 Family - UART not working properly with CSD
I am using hardware UART (RX8 or TX8 UM) with CapSense CSD/SmartSense/CSDADC UM in CY8C21x34 family of PSoC 1 devices. My UART is not working properly.
Most probable cause is the clock input of RX8/TX8 UM. If the clock input is any of the VC1, VC2 or VC3 dividers, then the intended baud rate obtained from those clock sources for the UART will be destroyed during program execution. The reason being based on Resolution and Scanning speed CSD/CSDADC/SmartSense UM modifies VC1, VC2 and VC3 dividers. The information and details on how they impact can be found in the UM datasheet (below figure).
So if you set the input clock of RX8 as VC2 and fix a baud rate of 150 ksps (SysClk = 24MHz, VC1 = Sysclk/16; VC2 = VC1/10). With a CSD resolution of 12 bit and normal scan speed, your baud rate changes to 750 ksps (Sysclk = 24, VC1 = Sysclk/4, VC2 = VC1/8). And this happens when CSD_Start() API is called. Worser would be using SmartSense, where the values of these dividers are not exposed to user and they change with each sensor.
- Use external Clock option (ROW_INPUT_x lines) for the input clock and route the clock to a pin.
- If using CSD/CSDADC, then based on the resolution and scan speed selected for the design calculate the baud rate in CY8C21x34 and tune the other end UART RX/TX to the baud rate obtained.
This bug is not confined to UART, it is valid for all the sources from digital block to interrupts like VC3 ISR which uses these system clock dividers. UART was taken as an example as it is the most common issue faced by customers trying to communicate the CSD button status over UART lines.
Please feel free to add your thoughts on other possible workarounds too.