generation of the clock | Cypress Semiconductor

generation of the clock

Summary: 3 Replies, Latest post by Holger Wech on 08 Mar 2017 06:33 AM PST
Verified Answers: 1
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 I am using the S6E2CC series controller i want  to generate the clock from the timer module if any done this can you explain me (i want to generate the 16 ,25, 50 mhz frequency),

Best regards 


bhwj's picture
Cypress Employee
66 posts


You can use a timer to divide the clock and output the signal on a pin but you need to GPIO Output Characteristics for the max output freq supported in the device datasheet.

You can get the driver library here :



we wants to generate the ethernet clock out from the ECOUT pin in the S6E2CC controller to feed to the PHY, Also what are the changes we need to make to send a packet through the ethernet , we are using the stack given by th you.

howe's picture
Cypress Employee
21 posts

have you seen these examples?

The ECOUT clock module can be enabled with symbol EMAC_ECOUT in emac_user.h.
But ... the jitter tolerance may be out of spec for most PHYs, so it is not recommended.




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