Question on the Design Challenge | Cypress Semiconductor
Question on the Design Challenge
I may be interested in participating in the challenge, but need some clarification on the resources.
If one makes it to the stage to receive a dev kit, what chip will it be, how much GPIO will the dev kit provide?
The design I anticpate may require up to 24 digital I/O pins, plus 8 Analog input pins, a couple of DAC outputs, and maybe a couple of event timer input pins. Maybe even another 13 I/O for a graphics LCD display. Will the dev kit be adequate to fulfill this?