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Question on the Design Challenge | Cypress Semiconductor

Question on the Design Challenge

Summary: 1 Reply, Latest post by Stub for 2575603 on 16 Dec 2010 04:40 PM PST
Verified Answers: 0
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MrTG17's picture
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I may be interested in participating in the challenge, but need some clarification on the resources.

If one makes it to the stage to receive a dev kit, what chip will it be, how much GPIO will the dev kit provide?

The design I anticpate may require up to 24 digital I/O pins, plus 8 Analog input pins, a couple of DAC outputs, and maybe a couple of event timer input pins. Maybe even another 13 I/O for a graphics LCD display. Will the dev kit be adequate to fulfill this?




Stub for 2575603's picture
99 posts

The kit we are going to use is the CY8CKIT-050 PSoC 5 Development Kit.  This kit is not offered online yet, so we don't have the webpage for it up yet.


It features a CY8C5588AXI-060ES1 device.  This device has 62 GPIO (analog & digital), 8 SIO (high-current digital) and 2 USBIO (USB or limited digital).  The board has multiple headers that connect to free IO so it's easy to interface it to external devices.  The board has 50+ I/O connected to the header.


It looks like a smaller version of our CY8CKIT-001 PSoC Development Kit.  The processor modules go away, and instead of having 3 expansion board headers (Port A, Port B, Port C) it only has 2 (Port D and Port E).  The expansion headers are the same form-factor.



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