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PSoC5 ADC eoc signal question | Cypress Semiconductor

PSoC5 ADC eoc signal question

Summary: 2 Replies, Latest post by Gautam Das on 08 Mar 2011 02:54 AM PST
Verified Answers: 0
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Schurtz's picture
23 posts


I try to use EOC signal of ADC as trigger, but it failed. Then I put the EOC on output pin, and capture by Oscilloscope. EOC is hi instead of a pulse.

API ADC_1_IsEndConversion() polling indicates the convertion works well. EOC signal is hi, not toggled.

Can you help? Attached my schematic in experiment

Schurtz's picture
23 posts


I can describe it detailly. 

Firstly, I try to use EOC rising edge to trigger an IRQ every time ADC convertion complete,  but only the first time ADC completion can trigger the IRQ. Then I connect the EOC to an output pin, and capture by Scope, I found the signal kept high instead of pulse.


dasg's picture
Cypress Employee
730 posts

Hi Schurtz,


This issue has been documented in the PSoC 5 errata.

It is as follows:

End-of-conversion (EOC) is signaled by a status register bit, decimator interrupt, decimator DMA, and DSI
routable signal. The DSI routable signal does not work. The CPU can poll the status register bit or use the
decimator interrupt or decimator DMA.

The ADC end-of-conversion (EOC) output of the PSoC Creator component can only be used to route to one
DMA channel. The EOC output cannot be used to route through the DSI routing to any other digital resources.
The decimator DMA route bypasses the DSI routing avoiding this issue. The decimator interrupt integrated
into the PSoC Creator component also bypasses the DSI routing. All other possible EOC connections require
DSI routing.

The CPU can poll the EOC bit in the status register or use the decimator interrupt to signal the digital system
using firmware and a control register.

Silicon revision fix available in ES2.

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