How To Debug a Verilog component which uses Cypress "extensions" | Cypress Semiconductor
How To Debug a Verilog component which uses Cypress "extensions"
I am working on my design which should be based on the supplied B_UART (v1.5). Being without hardware for now and later even with hardware - is there any way to simulate/debug the components behaviour without flashing it to the PSoC? I have access to ModelSim, but can't find any ressources on how to test a Verilog-based design which makes heavy use of all the Cypress extensions in ModelSim or some other Verilog simulator!?