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How To Debug a Verilog component which uses Cypress "extensions" | Cypress Semiconductor

How To Debug a Verilog component which uses Cypress "extensions"

Summary: 2 Replies, Latest post by kiku on 15 Feb 2011 11:23 AM PST
Verified Answers: 0
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-Robert-'s picture
3 posts


I am working on my design which should be based on the supplied B_UART (v1.5). Being without hardware for now and later even with hardware - is there any way to simulate/debug the components behaviour without flashing it to the PSoC? I have access to ModelSim, but can't find any ressources on how to test a Verilog-based design which makes heavy use of all the Cypress extensions in ModelSim or some other Verilog simulator!?

Any ideas?

Best regards


dasg's picture
Cypress Employee
730 posts

Hi Robert,


The files with .v extension can be tested on simulators like Modelsim.

But the Datapath implementation which is used in the creation of components like UART cannot be tested on the simulators. Equivalent verilog code can be written to perform the datapath's operation which can be simulated.

Test bench has to be written to provide the inputs and necessary clock.

Other freeware such as ICARUS can also be used for the purpose of simulation. Do make sure that the syntax of the verilog code matches with that of the standard.


If Debugging of the verilog code can be done, then a symbol can be created for the component, with required pins. The project containing this component can be executed in "debug" mode and output can be probed from the pins on the oscilloscope.

Control Register data can be used as clock by toggling appropriately. 




kiku's picture
Cypress Employee
64 posts

Hi Robert,


As Gautam told, it is not so easy to debug codes written in Verilog. But you can take out those signals and use Status registers externally to see the functionality. But if it is more of timing issues, then better use Modelsim to simulate.




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