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Hardware mux timing | Cypress Semiconductor

Hardware mux timing

Summary: 3 Replies, Latest post by Bob Marlowe on 17 Sep 2016 08:41 AM PDT
Verified Answers: 1
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jasonkahana_1482786's picture
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22 posts

I am trying to design a circuit that oscillates at ~48 kHz using hardware muxes and clocks.  A picture is attached.  PSoC lets me build this design using 2 clocks that are synched on the two muxes.  (Master CLK is 48 MHz).  It keeps giving me a Warning 1350:Asychronous paths exist from clock2(routed) to Clock1. 

 

Does anyone know why this is happening and how to resolve it?

Thanks!

jk

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user_1377889's picture
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10119 posts

I usually tried using a pulse sync component.

 

Bob

jasonkahana_1482786's picture
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22 posts

Is that a PWM?

user_1377889's picture
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10119 posts

No, it is a pulse sync component. Creator -> Component catalog -> Digital -> Utility -> Sync

 

Bob

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