Tracking Skew of PLLs | Cypress Semiconductor
Tracking Skew of PLLs
Tracking skew can be defined as the deviation of the output of the PLL from its input.
We can expect the feedback signal to be stable as any variations there itself can cause instability with the locking and have the PLL working in Acquisition and tracking mode which are the two states of a PLL: phase-locked or acquiring lock. Any larger change to the frequency and phase to the Reference or Feedback is going to make the clock lose its lock and relock to the new frequency and phase. Cypress usually does not define and measure the tracking skew for the devices and provide as a value. It should be noted that PLLs are normally capable of tracking long-term jitter. PLLs, by design, are incapable of tracking cycle-to-cycle jitter, because the PLL response time is typically slow. When the modulation occurs at a rate and level that is too difficult for a PLL to track, the PLL may give a “best-effort” tracking which is referred to as tracking skew.
Tracking is synonymous with the locked condition and simply describes the extent to which the loop can follow variations in the input clock frequency. PLLs operate on the phase of signals and therefore are susceptible to changes in the clock edges on the inputs. The transient response of a PLL is generally a very complex, non-linear process. In general terms, the PLL will follow the presence of a slowly occurring signal at the input and does not react to rapidly occurring transitions (frequencies outside of the PLL’s loop bandwidth).
So with the Tracking skew, cascaded PLLs can have an adverse effect on the amount of skew exhibited. Modulations and excessive input noise that are sometimes created by jitter peaking, can lead a phase-locked loop into a condition of instability that results in less than optimal output conditions.