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Power Supply Decoupling and Layout Significance in Buffers | Cypress Semiconductor

Power Supply Decoupling and Layout Significance in Buffers

Summary: 0 Replies, Latest post by Stub for 2594006 on 10 Aug 2011 07:38 AM PDT
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Even if there is no ripple at the supply source, you will see ripple at the Vdd pin of a Buffer when its outputs are switching. The switching outputs create large di/dt which causes Vdd and Vss noise both inside the chip and externally. That is why the external decoupling is so important, because only local capacitors are capable of servicing those large current transients. Also, inductance on Vss and Vdd must be minimized. When a ferrite bead is added to the Vdd path, it increases the Vdd path inductance. This is good for EMI, but it makes it that much more important that very good decoupling be provided between the ferrite and the chip.


If still some incorrect oscillation is happening, it is likely that the poor VDD layout is playing a major roll in the problem. The VDD trace to the nearest capacitor should not be very narrow and should not be long with a Via. It’s always recommended that decoupling capacitors be placed as close as possible to the VDD pin, and that it is connect to the pin with a wide trace. So most of the VDD noise comes from the device itself, due to the multiple outputs switching, which makes good decoupling very important.


Check for more details the following chapters of Perfect Timing II book available at:


Chapter 5 – Power Supply Filtering

Chapter 6 – PCB Layout Considerations

Chapter 8 – Bypass Capacitors

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