You are here

Glitch Tolerance at Input of CY2308 | Cypress Semiconductor

Glitch Tolerance at Input of CY2308

Summary: 0 Replies, Latest post by Stub for 2594006 on 16 Sep 2011 05:57 AM PDT
Verified Answers: 0
Log in to post new comments.
Stub for 2594006's picture
135 posts

The CY2308 was not designed as a Fail Safe device. The Pll of the CY2308 will not lose lock as a consequence of the oscillator being pulled by a few hundred PPM. The CY2308 PLL will be able to track any low frequency variations in the reference input and will filter out any high frequency variations greater than the loop bandwidth.

This glitch operation had been tested for different reference frequencies: 33MHz, 66 MHz, 100 MHz, and 133MHz. The signal at the PLL output remained for the minimum of 2.3uSec after the input signal was shut off. This free running output frequency drifted slowly but no glitch was observed in any case. The measurement was under 3.3V power supply room temperature. So accordingly, it would not lose lock with a single glitch.

Log in to post new comments.