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Ferrite Bead Go/No-Go for Filtering Clock Buffer Power Supplies | Cypress Semiconductor

Ferrite Bead Go/No-Go for Filtering Clock Buffer Power Supplies

Summary: 0 Replies, Latest post by Stub for 2594006 on 14 Jun 2011 06:38 AM PDT
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Ferrite beads are used in power supply filtering as they reduce the injection of clock noise into the main VDD supply. At the same time they also increase ripple in Cypress clock devices. It would also filter the necessary signal current and hence ferrite bead is usually not recommended to be used. When a ferrite bead is added to the Vdd path, it increases the Vdd path inductance. This is good for EMI, but it makes it that much more important that very good decoupling be provided between the ferrite and the chip.

As everyone is aware, Ferrite beads offer a level of filtering to produce the absolute best quality in signals. It is very difficult to determine which ferrite bead will perform the best based on the manufacturers specifications. By using data from a test environment, a bead that will filter the noise can be selected. We have detailed analysis in Chapter 5 of our Perfect Timing II book, available on our website at: that gives general as well as specific guidelines that may or may not be given in the device datasheets. Although it is difficult to select which bead will perform best, the analysis and recommendations presented in this chapter provides the necessary guideline information.

When quality of the voltage supply degrades, so does signal integrity. Noise in the supply will affect jitter and skew in clock buffers. Essentially, one may want to use bypass capacitors (usually of 0.1 uF) attached to each pair of power and ground pins placing the bypass capacitor as close to the device pins as possible.

Check the Perfect Timing II book that also discusses Power Supply Filtering.


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