Clock Buffer Behavior below the Specified Minimum Input Frequency | Cypress Semiconductor
Clock Buffer Behavior below the Specified Minimum Input Frequency
Currently Cypress does not have much buffer devices in the lower MHz range or KHz range. There is CY2302 amongst zero delay buffers that can go down to 5MHz.
Most of the zero delay buffers have a minimum input frequency of 10MHz. So operation with input reference below 10MHz minimum of the device cannot be guaranteed. If a PLL operates near the point of instability, the PLL lock time can become excessive.
10 Mhz is a guard band of the minimum frequency. When this frequency is reached, the zero delay buffers usually will go into power down mode as it would when there is no input. There is no guarantee on any other specifications likes duty cycle, jitter, lock times etc. when the input frequency specification range is violated at the lower end.